1 Design Purpose

This course project designs a two-stage operational amplifier that uses an external ideal current source
as bias to drive an external capacitor. The entire circuit schematic is shown in the following figure.
Finally, the trainees are required to conduct circuit simulation, layout design, as well as DRC, LVS and
PEX checks on the designed amplifier. The design targets are as follows. IBIAS and all parameters
inside op-amp is adjustable.

Parameters	Design Targets (Post-Layout Simulation)
Supply voltage (VDD)	3.3V
Common-mode input voltage (Vcm, in)	1.65V
Common-mode output voltage (Vcm, out)	Between 1.6~1.7V
DC gain (Gain)	>5000 (>74dB)
Gain-bandwidth product (GBW)	>30MHz
Phase margin (PM)	>60°
Power consumption (Idc)	<200uA
FOM = GBW/Idc	>0.15 MHz/uA, as large as possible
Op-amp layout drawing	Rectangle, as compact as possible
Op-amp layout verification	DRC, LVS, PEX

2 Design Process

2.1 Determine the Circuit Structure

For such design parameters, I design a two-stage operational amplifier with five transistors OTA in the
first stage and a common source stage in the second stage. As shown in figure 2-1, the leftmost is the
bias circuit, the middle is the first stage amplifier, which provides high gain, and the second stage is
the common source stage, which provides large output swing.

2.2 Analysis of Low Frequency Characteristics of Circuit

For the two-stage amplifier of the above structure, the small signal model of the circuit is extracted
first, as shown in figure 2-2.

The transconductance of the first stage amplifier is equal to the transconductance of the input transistor
M_1,2, that is, 𝐺_𝑚1 = 𝑔_𝑚1 = 𝑔_𝑚2, and the output resistance of the first stage is 𝑅₁ = (𝑟_𝑂2||𝑟_𝑂4), so the
low frequency gain of the first stage is:

$$A_{1} =G_{m1} R_{1} =g_{m1} (r_{O2} ||r_{O4})$$

The transconductance of the second stage amplifier is equal to the transconductance of the input
transistor M₆, that is, 𝐺_𝑚2 = 𝑔_𝑚6, and the output resistance of the second stage is 𝑅₂ = (𝑟_𝑂6||𝑟_𝑂7), so
the low frequency gain of the second stage is:

$$A_{2} =-G_{m2} R_{2} =-g_{m6} (r_{O6} ||r_{O7})$$

The total low frequency gain of the two-stage operational amplifier is:

$$A_{0} =A_{1}A_{2} =-g_{m1}g_{m6}(r_{O2}||r_{O4})(r_{O6}||r_{O7})$$

2.3 Analysis of Frequency Characteristics of Circuit

𝐶₁ represents the total capacitance of the input node to the ground, that is:

$$C_{1} =C_{DB2}+C_{DB4}+C_{GD2}+C_{GD4}+C_{GS64}$$

𝐶₂ represents the total capacitance of the output node to the ground, that is:

$$C_{2} =C_{GD7}+C_{DB6}+C_{DB7}+C_{L}$$

Because the poles provided by the first stage and the second stage are close to each other, it is not
convenient to regard it as a single-stage point system, so it is difficult to control the stability, so it is
necessary to carry out frequency compensation and connect a Miller compensation capacitor 𝐶_𝐶
between the input and output of the two stages to split the two poles so as to make the system more
stable. List the KCL equation of the circuit column, there are:

$$\left\{\begin{matrix}G_{m1} V_{id} +\frac{V_{i2}}{R_{1}} +V_{i2} sC_{1} +(V_{i2}-V_{O})sC_{C}=0 \\G_{m2} V_{i2} +\frac{V_{O}}{R_{2}} +V_{O} sC_{2} +(V_{O}-V_{i2})sC_{C}=0\end{matrix}\right.$$

The solution is:

$$\frac{V_{O}}{V_{id}}=\frac{G_{m1}(G_{m2}-sC_{C})R_{1}R_{2}}{as^{2}+bs+1}$$

$$a=[C_{1}C_{2}+C_{C}(C_{1}+C_{2})]R_{1}R_{2}$$

$$b=C_{1}R_{1}+C_{2}R_{2}+C_{C}(G_{m2}R_{1}R_{2}+R_{1}+R_{2})$$

By using the principal pole approximation and the relative size relationship of each parameter, I can
obtain two poles and one zero of the circuit approximately:

$$\{\begin{array}{c}{\omega }_1=\frac{1}{g_{m6}{R}_1{R}_2{C}_C}\\ {\omega }_2=\frac{g_{m6}}{G_L}\\ {\omega }_Z=\frac{g_{m6}}{C_C}\end{array}$$

Therefore, the gain bandwidth product can be deduced:

$$GBW=\frac{A_{0}\omega_{1}}{2\pi}=\frac{g_{m1}}{2\pi C_{C}}$$

2.4 Determine 𝑪_𝑪 by Frequency Compensation

From the above analysis, we can find that there is a zero in the right half plane. In order
to make it have no effect in the frequency range we are interested in, I let 𝜔_𝑍 ≥ 2𝜋 ∙
10𝐺𝐵𝑊, through calculation, we can get 𝑔_𝑚6 ≥ 10𝑔_𝑚2.

Then we can get the phase relationship between the output and the input:

$$\angle \frac{v_{O}}{v_{in}}=-tan^{-1}(\frac{\omega}{\omega _{z}})-tan^{-1}(\frac{\omega}{\omega _{1}})-tan^{-1}(\frac{\omega}{\omega _{2}})$$

According to the design parameters, the phase margin should be greater than or equal to 60 degrees,
so there are:

$$PM=180-tan^{-1}(\frac{2\pi GBW}{\omega {z}})-tan^{-1}(\frac{2\pi GBW}{\omega {1}})-tan^{-1}(\frac{\omega 2\pi GBW}{\omega {2}})$$

$$=180-5.71-89.2-tan^{-1}(\frac{\omega 2\pi GBW}{\omega {2}})\ge 60$$

We can obtain: 𝐶_𝐶 ≥ 0.214𝐶_𝐿 = 2.14pF.Then after the simulation I adjusted it to 2.5pF.

2.5 Determine the Channel Length of the Transistor

Using umc18mmrf process library, the minimum channel length of the transistor is 180nm, generally
more than twice the minimum length, here I choose L = 1um (L=340nm for M_1,2 , L=700 for M₆)

2.6 Determine the Current by the Conversion Rate

When there is a large positive step input at the input, M₂ turns off, and all the currents flow through
M₁. Because the current of M₃ is equal to that of M₁ and is mirrored to M₄, the current of M₄ can only
flow out through 𝐶_𝐶, so in this case, the conversion rate:

$$SR=\frac{I_{DS5}}{C_{C}}$$

Similarly, when there is a large negative step input at the input, M₁ is off, and all the currents flow
through M₂. Because the current of M₃ is equal to that of M₁ and is mirrored to M₄, the current of M₂
can only be driven by M₆ to flow from 𝐶_𝐶. While M6 needs to drive 𝐶_𝐿 at the same time, in this case,
the conversion rate:

$$SR=\frac{I_{DS7}-I_{DS6}}{C_{L}}$$

There are no requirements related to the conversion rate in this course design, but the power
consumption is required to be less than 200uA, so I chose 𝐼_𝐷𝑆5 = 70μA and 𝐼_𝐷𝑆7 = 90μA here to
make the conversion rate as fast as possible.

2.7 Determine the Size of M_1,2 by GBW

GBW is required to be greater than 30MHz, so it can be calculated as follows.

$$GBW=\frac{g_{m1}}{2\pi C_{C}}$$

We can obtain: 𝑔_𝑚1,2 = 250𝜇 . By bringing 𝜇_𝑛𝐶_𝑜𝑥 and 𝜇_𝑝𝐶_𝑜𝑥 (Obtained separately in Cadance
simulation) in the formula, we can calculate:

$$g_{m1}=\sqrt{2I_{D1}\mu_{n}C_{ox}(\frac{W}{L})_{1}}$$

$$(\frac{W}{L})_{1,2}=141.2$$

2.8 Determine the Size of M_3,4 by Common-mode Input Voltage

The maximum common-mode input voltage is limited by M_3,4. Because they are connected by diode,
M_3,4 must be saturated when they are in the on state, so the drain voltage of M₁ is 𝑉_𝐷𝐷 − 𝑉_𝐺𝑆3. At the same time, to ensure that M₁ is also saturated, the maximum value of common mode input can be
expressed as 𝑉_𝑐𝑚(+) = 𝑉_𝐷𝐷 − 𝑉_𝐺𝑆3 + 𝑉_𝑇𝐻1. Can be obtained from the square law:

$$V_{GS3}=\sqrt{\frac{2I_{DS3}}{\mu {p}C{ox}(\frac{W}{L})_{3}}}+|V_{TH3}|$$

$$V_{cm(+)}\le V_{DD}-\sqrt{\frac{2I_{DS3}}{\mu {p}C{ox}(\frac{W}{L})_{3}}}-|V_{TH3}|+V_{TH1}$$

Calculated by substituting the curriculum design parameters：

$$(\frac{W}{L})_{3,4}=24$$

2.9 Determine the Size of M₅ by Common-mode Input Voltage

The minimum common mode input voltage is limited by M₅, because M₅ is used as a current source,
so M₅ must be biased in the on state. To ensure that M₅ is in a saturated state, as long as the drain
voltage of M₅ is offset, the drain voltage should be more than twice the overdrive voltage. When M₁
is working normally, the voltage relationship can be expressed as follows:

$$V_{cm(-)}\ge V_{GS1}+V_{OD5}$$

$$V_{cm(-)}\ge \sqrt{\frac{2I_{DS1}}{\mu {p}C{ox}(\frac{W}{L})_{1}}}+V_{TH1}$$

Calculated by substituting the curriculum design parameters：

$$(\frac{W}{L})_{5}=12$$

3.10 Determine the Size of M₆ by Phase Margin

𝑔_𝑚6 ≥ 10𝑔_𝑚2 is determined in the frequency compensation, the circuit is connected first and then the
simulation is carried out, as shown in figure 2-3, we can find 𝑔_𝑚2 ≈ 250𝑢, so 𝑔_𝑚6 ≈ 2.5𝑚. After
many simulations and adjustments, we can determine:

$$(\frac{W}{L})_{6}=74.3$$

2.11 Determine the Size of M₇ by DC Current

After many simulations and adjustments, we can determine:

$$(\frac{W}{L})_{7}=20, (\frac{W}{L})_{8}=2$$

2.12 Summarize the Size Parameters

Devices	Parameters
M1,2	(W/L)1,2 = 141.2
M3,4	(W/L)3,4 = 24
M5	(W/L)5 = 12
M6	(W/L)6 = 74.3
M7	(W/L)7 = 20
M8	(W/L)8 = 2
𝑅𝑟𝑒f	8 kΩ
𝐶𝐶	2.5 pF

3 Simulation Analysis (Pre-Layout)

3.1 DC Analyses

The red line represents the output voltage. By placing the Marker, it can be measured that when the input voltage is 1.65V, the output voltage is approximately 1.65V, which basically meets the common mode output voltage requirements of 1.6-1.7V.

3.2 AC Analyses

When the common mode voltage is 1.65V, the corresponding gain and frequency characteristics are shown in figure 3-2. The low frequency gain is about 76.37dB. When the gain is about 0dB, the phase is about 65.3°, so the phase margin is 65.3°. At this time, the frequency is 32.46MHz, which just meets the requirements of GBW.

Calculator tool can accurately calculate the parameters of simulation results. Here is the result.

Devices	Simulation Result
DC operation point	1.65V
DC gain (GAIN)	76.37dB
Gain-bandwidth product (GBW)	32.46MHz
Phase margin (PM)	65.3°
Power consumption (Idc)	170.9uA
FOM = GBW/Idc	0.19MHz/uA

4 Layout Design (DRC/LVS/PEX Included)

4.1 Place the Components

Place the components in the layout and place the dummy tubes at both ends of the components to avoid the influence of noise on the critical signal in the chip and ensure the manufacturability at the same time. Note that the dummy tubes should be the same parameters as the MOSFET. In addition, all pins of NMOS must be grounded, and all pins of PMOS must be connected to VDD.

4.2 Through-hole Connection of Metal Layer

4.3 Guarding

PMOS are protected by n-guarding to VDD, and NMOS are protected by p-guarding to GND.

4.4 Connection

Then connect the other components in sequence, consider the matching of M3, M4 and M6, as well as
the matching of M5, M7, and M8. Then add the IP label again.

4.5 Layout Verification: Calibre DRC, LVS, and PEX

No.	Layout Net	Source Net	R Count	C Total (10-15F)	CC Total (10-15F)	C+CC Total (10-15F)
1	IBIAS	IBIAS	125	15.95	22.62	38.57
2	2	NET2	226	8.438	22.49	30.93
3	GND	GND	690	12.37	27.80	40.17
4	VIN	VIN	64	2.285	3.446	5.731
5	VIP	VIP	61	2.762	3.156	5.918
6	VDD	VDD	575	8.039	26.27	34.31
7	7	NTE1	153	4.417	5.864	10.28
8	8	NET4	21	1.017	7.405	8.422
9	OUT	OUT	195	18.56	33.75	52.31
10	10	NET3	154	3.051	8.296	11.35

5 Post-Layout Simulation Results

5.1 DC Analyses

The red line represents the output voltage. By placing the Marker, it can be measured that when the
input voltage is 1.65V, the output voltage is approximately 1.779V. Compared to the post-layout
simulation results, the parameters have increased.

5.2 AC Analyses

When the common mode voltage is 1.65V, the corresponding gain and frequency characteristics are
shown in figure 6-2. The low frequency gain is about 76.38dB. When the gain is about 0dB, the phase
is about 63.5°, so the phase margin is 63.5°. At this time, the frequency is 32.06MHz, which meets the
requirements of GBW.

Calculator tool can accurately calculate the parameters of simulation results. Here is the result.

Devices	Simulation Result (pre-layout)	Simulation Result (post-layout)
DC operation point	1.65V	1.7V
DC gain (GAIN)	76.37dB	76.38dB
Gain-bandwidth product (GBW)	32.46MHz	32.06MHz
Phase margin (PM)	65.3°	63.5°
Power consumption (Idc)	170.9uA	170.8uA
FOM = GBW/Idc	0.19MHz/uA	0.19MHz/uA

6 Summary

In this modular design process, I completed the entire process of a op-amp from “pensile-to-paper”,
simulation, layout, to post simulation, and gained a lot from it.
After this learning and practical experience, I have developed a more systematic and intuitive
understanding of the entire operational amplifier, resolving many questions I had from my prior
module set studies. Additionally, this course has significantly enhanced my layout skills, laying a
stronger foundation for my future studies.